DLR datasheet, DLR datasheets and manuals electornic semiconductor part. FSDLRL, FSDLRL, FSDLRL, FSDLRL and other. Datasheet search engine for Electronic Components and Semiconductors. DLR data sheet, alldatasheet, free, databook. DLR parts, chips, ic. DLR datasheet,Page:3, FSDLRN Pin Definitions Pin Number 1 Pin Name GND Pin Function Description Sense FET source terminal on primary side .
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This device is an integrated high voltage power switching regulator which combine an avalanche rugged Sense FET with a current mode PWM control block. The feedback voltage pin is the non-inverting input to the PWM comparator. There is a time delay while charging between 3V and 6V using an internal 5uA current source, which prevents false triggering under transient conditions but still allows the protection mechanism to operate under true overload conditions.
Although connected to an auxiliary transform. Because excess energy is provided to the output, the output voltage may exceed the rated voltage before the over load protection is activated, resulting in the breakdown of the devices in the secondary side. If this pin is tied to Vcc or left floating, the typical current limit will be 1. Drain to Source Peak Current Limit. Internal Soft Start Time. In case of malfunc- tion in the secondary side feedback circuit, or feedback loop open caused by a defect of solder, the current through the opto-coupler transistor becomes almost zero.
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The integrated PWM controller features. In order to prevent this situation, an over voltage protection OVP circuit is employed. Frequency Change With Temperature 2. Positive supply voltage input. In order to avoid undes- ired activation of OVP during normal operation, Vcc should be properly designed to be below 19V. In case of malfunc.
Current Limit Delay 3. This pin connects directly to the rectified AC line voltage source. Vcc instead of directly monitoring the output voltage. Maximum practical continuous power in an open frame.
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In addition to start-up, soft- start is also activated at each restart attempt during auto- restart and datqsheet restarting after latch mode is activated. The voltage across the resistor is then compared with a preset AOCP level.
Once the Vcc reaches 12V, the internal switch is disabled. Turn Off Delay Time. The voltage across the resistor is then compared with a. Adapt- Open Adapt- Open.
The typical soft start time is 15msec, as shown in figure 8, where progressive increments of Sense FET current are allowed during the start-up phase. When compared to a discrete. It also helps to prevent transformer saturation and. Pin to adjust the current limit of the Sense FET. Delay current 5uA charges the Cfb. In order to avoid undes. eatasheet
DLR Datasheet PDF – Fairchild Semiconductor
UVLO upper threshold 12V that the internal start-up switch opens and de. A feedback voltage of 6V trig. It also helps to prevent transformer saturation and reduce the stress on the secondary diode.
Home – IC Supply – Link. It is not until Vcc reaches the. Pin Configuration Top View 3. Over load protection 4. Here, pulse by pulse. Typical continuous power in a non-ven. This device is an integrated. Startup Voltage Vstr Breakdown.
A feedback voltage of 6V trig- gers over load protection OLP.
There is a time delay while charging. The integrated PWM controller features include: Once the Vcc reaches. Although connected to an auxiliary transform- er winding, current is supplied from pin 5 Vstr via an internal switch during startup see Internal Block Diagram section.
The Drain pin is designed to connect directly to the primary lead of the trans.