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Limits. Symbol. Parameter. Conditions. −40°C. +25°C. +85°C. Units. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. IL. Quiescent Device. VDD = V. Data sheet acquired from Harris Semiconductor. SCHSC – Revised September The CDUB types are supplied in lead hermetic dual-in- line. Order Number CD C National Semiconductor Corporation . This datasheet has been downloaded from: Datasheets for.

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Try increasing the frequency and see at what frequency the inverter has trouble completing high to low and low to high transitions.


Estimate Vtn from Ids-Vgs curves. Clean up Previous datashset 7.

The output is pin 12,13, or 5. Remember that chips 2 and 4 shown datashee Figure 8 need Vdd and Ground connections. Connect pins 2,9 to CH0, and pins 4,11 to CH1.

During the transparent phase of the latch, i. A low budget way to avoid static discharge is to ground yourself before touching an IC. The capacitor will begin to charge. Normally one would use anti-static mats and wrist straps when working with static sensitive electronics.

Therefore, this circuit is an oscillator. Compare measured Vdsat with 1st order theory, i.

You should see a graph similar to the one shown below in figure 4. This is the opaque phase of the latch.


8. CMOS Logic Circuits — elec documentation

We will test the two transmission gates by connecting FGEN to the input, and connecting a load of 1k on either output sides. Observe the DIO8 pin. CMOS inverter schematic for voltage transfer measurement.

The two transmission gates work in tandem to cd datasheet the D-latch. When specifying wiring between the pins of an IC, engineers often use a shorthand for connections.

Output of first inverter. Proceed as shown in Figure 6. Set the function generator to output a Hz sine wave, 5vpp, 2. At what input voltage does the output transition to logic low? For example, consider 22,5,7 ; 1,3, Describe the differences between the screenshots other than that they are inverted. This is because CMOS logic requires a voltage input of 0-Vdd and the function generator always provides a waveform with a dc component of 0 V.

A steady high should appear. Therefore, this circuit is datashret oscillator. Construct the circuit shown in figure 9 using the pin-level diagram from the pre-lab. You may find the diagram shown below in figure 13 helpful. Normally one would use anti-static mats and wrist straps when working with static cd datasheet electronics.


Each pair shares a common gate pins 6,3, Build a double transmission gate using a new CD chip as shown in Figure 6. It should look as shown below in Figure 5. Such information will be used to improve this and future labs and your experience will help future students.


For example, a single CD can be used to make a chain of 3 inverters, an inverter plus two transmission gates, or a complex logic gate. Navigation index next previous elec 1. We will use the D-latch constructed in the previous section as the master latch in our master slave D flip flop. For the complete circuit you will need fd CD chips. D is transmitted to the output Q through the first transmission fd4007 and the two-inverter cascade.

Your output should look similar to figure It should look as shown in Figure 8. Now insert two inverter chain you built earlier and retained from the first exercise to the circuit you have just built. Attach screen shots for working frequencies, and for too high frequencies such that transitions between 0 and VDD are not complete.

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Schematic of D latch. Fatasheet the logic function implemented by the following connections to a CD Ids-Vds curves for multiple gate-to-source voltages Vgsfrom which we can observe linear and saturation operation regions.

What to do in lab report Show 3 screen shots of inverter outputs. Datasheeh, the input to the first inverter is close to the voltage at node C.