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BURIED WORDLINE PDF

Before Qimonda’s unfortunate demise last year, they delivered an impressive paper at IEDM [1] describing a “buried wordline” (BwL). Memory chip supplier Qimonda says it is about to begin commercial production of DRAM chips using its new “Buried Wordline” technology. Provided are a semiconductor device having a buried word line structure in which a gate electrode and a word line may be buried within a substrate to reduce.

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The metal gate electrode 20 can serve as a gate electrode and a word line.

Winbond Adopts Qimonda’s Buried Wordline Technology – Metal Gates Come to DRAMs | Siliconica

The oxide layer formed on the top surface of the substrate when forming the gate insulating layer may be removed using a conventional method e. A method of fabricating a semiconductor device having a buried word line structure may comprise forming a device isolation layer defining an active region in a semiconductor wirdline, forming a trench for forming one or more recess channels in the active region, forming a gate insulating layer on the surface of the trench, forming a gate electrode layer on the surface of the gate insulating layer, and forming a buried word line burying the trench on the surface of the gate electrode layer.

Like reference numerals refer to like elements throughout. In example embodiments, the gate electrode layer may be formed to have a thickness within a range of about 1 to about 10 nm. Alternatively, the gate electrode layer may be recessed together with the second word line layer.

Materials used to form the gate electrode layer biried be described in detail below. Thus, the dordline surfaces of the gate electrode layer and the gate insulating layer may also be recessed within the substrate and may be formed such that the capping layer caps simultaneously the recessed regions of the gate insulating layer and the gate electrode layer and the recessed region of the buried word line In example embodiments, forming of the buried word line may include forming a word line layer on the substrate so as to bury the trench, polishing the word line layer using chemical mechanical polishing CMP and an etch-back method which uses a dry etch to expose the surface of the substrate, and recessing the polished word line layer into the burisd.

The gate electrode layer may be formed so as to have a thickness within a range of about 1 to about 10 nm, for example, below 5 nm. In example embodiments, the trench may be formed to have a width within a range of about 10 to about nm.

The buried word line may comprise any one selected from the group consisting of tungsten Waluminum Alcupper Cumolybdenum Motitanium Titantalum Taand ruthenium Ruor a combination thereof.

Accordingly, when the gate electrode layer includes polysilicon and is formed to a thickness of about 5 nm, the atomic layer deposition may be carried out using the Si 3 H 8 gas. The buried word line may be formed by recessing the polished word line layer into the substrate using a partial etch process.

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A trench forming a recess channel within the active region defined by the device isolation layer may be formed. The budied buried word line may be formed wordine forming a first word line layer not shown on the substrate so as to bury the trench Therefore, it is to be understood that the foregoing nuried illustrative of example embodiments and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims.

In example embodiments, the lower buried word line may include polysilicon. As described above, the electrical resistance of the word line of the buried word line composed of the lower buried word line and the upper buried word line may be lower when the upper buried word line includes silicide and metal material. Semiconductor devices including a field effect wotdline and methods of the same.

Method of forming semiconductor device and semiconductor device formed by the same.

6F2 buried wordline DRAM cell for 40nm and beyond

In addition, a description of forming layers within and on the gate using deposition and etching techniques is also well known to those skilled in the art, and thus, omitted. The semiconductor device of claim 1wherein the upper buried word line includes at least one of tungsten Burieedaluminum AlCopper Cumolybdenum Motitanium Titantalum Taand ruthenium Ru.

In example embodiments, forming the lower buried word line may include forming a first word line layer on the substrate so as to bury the trench, polishing the first word line layer using chemical mechanical polishing and an etch-back method which uses a dry etch to expose the surface of the substrate, and recessing the polished first word line layer into the substrate to form the lower buried word line.

The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. M Year buriec fee payment: Non-volatile semiconductor memory device having vertical transistors with the floating and control gates in a trench and fabrication method therefor. And they are in volume production, we have also found them in bureid point and shoot camera. Wordlihe trench may be formed so as to have a width within a worvline of about 10 to about nm, for example, below 50 nm.

One other point was made by Qimonda before they went under, that this technology is particularly suitable for a cell shrink from the current 6F2 to a 4F2 format, enabling even worvline cost savings by reducing wordlie size. However, this is merely illustrative and thus, the upper buried word line is butied limited to these metals. The size of the recessed region of the gate insulating layerthe gate electrode layerand the buried word line may be equal to or maybe different from each other.

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The degradation of the oxide layers due to the occurrence of chlorine ions from applying the TiN layer, which is formed using a CVD or an atomic layer deposition ALD method, is one of the causes of the problems described above. The gate electrode layer may comprise polysilicon which may be formed using an atomic layer deposition method in which Si 3 H 8 may be used as a silicon source gas.

Semiconductor memory devices including vertically oriented transistors and methods of manufacturing such devices. Example embodiments provide a semiconductor device having a buried word line structure in which a gate electrode and a word line may be buried inside of a substrate, thereby reducing the height of the semiconductor device and the degradation of oxide layers due to the application of a TiN wordlie gate.

The buried word line may be formed using a chemical vapor deposition, a physical vapor deposition PVDor an atomic layer deposition method. In example embodiments, the gate electrode layer may be formed using a chemical vapor deposition CVD or an atomic layer deposition ALD method. As such, there may be less leakage current. The semiconductor device may comprise a semiconductor substrate defined by a device isolation layer and comprising an active region including a trench and one or more recess channels, a gate isolation layer on the surface of the trench, a gate electrode layer on the surface of the gate isolation layer, and a word line by which the trench may be buried on the surface of the gate electrode layer.

The upper buried word line may be formed of a material different from that of the lower buried word line. The lower buried word line may comprise polysilicon. As such, when the gate electrode and the word line are formed of only titanium nitride Tinthere may be an increase in leakage current. The upper buried word line may be formed of any one of tungsten Waluminum Alcupper Cumolybdenum Motitanium Titantalum Taand ruthenium Ruor a combination thereof.

Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.

Reference will now be made in buroed to example embodiments, examples of which are illustrated in the accompanying drawings. The lower buried word line may be formed of polysilicon. Example embodiments relate to a semiconductor device having a buried gate electrode and a method of fabricating the same. Dual work function bruied gate type transistor, method for manufacturing the same and electronic device having the same.

The buried word line may be formed using a chemical vapor deposition, a physical vapor deposition PVDor an atomic layer deposition ALD method. The first word line layer may then be polished using chemical mechanical polishing to expose the surface of the substrate