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The ADC/ADC/ADC/ADC are 8-bit successive approximation A/D converters Details, datasheet, quote on part number: ADC ADC/ADC/ADC/ADC 8-Bit High-Speed Serial I/O A/D products and disclaimers thereto appears at the end of this data sheet. An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical the end of the data sheet. .. ADC

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ADC Datasheet(PDF) – National Semiconductor (TI)

One converter package can now handle ground refer. Logical “1” Input Current. DI line is clocked into the MUX address shift register. This feature is most useful in single-supply applica. Logical “1” Output Voltage. The differential input of these converters actually reduces.

Life support devices or systems are devices or. Power Supply Current vs. LSB information is maintained for remainder of clock periods until CS goes high. ESD Susceptibility Note 6. The converter can be made to out. Zero-Shift and Span Adjust: SE is forced low the data is clocked out LSB first. Operating with Ratiometric Transducers. The voltage applied to the reference input on these convert.


Capacitance of Logic Inputs. Because the ADC contains only one differential input. Voltage at Inputs and Outputs. F capacitor is recommended. Logical “0” Input Voltage.

For absolute accuracy, where the analog input varies be. The analog inputs can be configured to operate in various. Digitizing a Current Flow. Differential inputs are restricted to adjacent channel pairs. In addition, input voltage spans. Two on-chip diodes are tied to each analog input see Block Diagram which will forward-conduct for.

The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four pins.

The DI and DO lines can be tied together and controlled. Logical “1” Input Voltage. This voltage does not have to be analog ground; it. N Package 10 sec. No power required remotely.

ADC08031 Datasheet PDF

The full-scale adjustment should be made [with the proper. The design of these converters utilizes a comparator struc. Data Valid Note This programmability is best illustrated by. MUX address selects which of the analog inputs are to be.

Capacitance of Logic Outputs. The guaranteed specifications apply only for the test conditions listed. The worst-case leakage current of?


ADC Selling Leads, Price trend, ADC DataSheet download, circuit diagram from

IRE TM serial data exchange standard for easy interface to the. The minimum value, however, can be quite. These ratings do not guarantee specific performance datssheet. After 8 clock periods the conversion is completed.

For devices offering guaranteed voltage ref. Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in see Block Diagram to allow.

Supply Voltage V CC.

During the conversion the output of the SAR comparator. Since the input configuration is under software control, it can. For example, channel 0 and channel 1 may be selected as a. Total unadjusted error includes offset, full-scale, linearity, multiplexer. The SARS line goes high at this time to signal that a con. To understand the operation of these converters it is best to. In the case that an available clock has a duty cycle outside of these limits.

Source resistance limitation is important with regard to the.